Network interface

ABSTRACT

A network interface is designed for two-wire reception via a serial bus and has a differential receiver which is connected to input lines. The network interface likewise has an element for recognizing error states on the bus lines. It is designed such that it changes into single-wire operation after recognizing the error state, in order to maintain the data traffic. In this case, one input line is connected to a fixed terminal potential. The terminal potential is in this case selected such that the magnitude of the potential difference between the two input lines is the same for both bit levels.

BACKGROUND OF THE INVENTION Prior Art

The invention is based on a network interface of for a serial bus havingat lest two bus lines. A network interface is already known from DE-OS38 26 774. The network interface described there is designed for use inthe so-called Controller Area Network (CAN). The CAN is a serial bussystem which is primarily designed for use in motor vehicles. In thiscase, the information is transmitted between a plurality of networksubscribers via a two-wire link. Each network subscriber contains anetwork interface. Each network interface is connected to the two-wirelink. Each network interface has a differential receiver whose inputsare linked to the two-wire link. In the event of one of the two signallines failing as a result of a short-circuit or interruption, two-wirereception is no longer possible. The network interface according toDE-OS 38 26 774 is designed such that it recognizes error states of theabove type and then switches over from two-wire reception to single-wirereception. For this purpose, it applies a fixed terminal potential toone input line of the differential receiver. If differential receptionis possible again subsequently to this, the terminal potential remainsconnected to the input line and information reception takes place viathe remaining signal line. In other cases, the terminal potential isapplied to the other signal line and the terminal potential isdisconnected from the first signal line. After this, informationreception can take place via the other signal line. In both cases, thesame terminal potential is applied to the respective signal line. Theterminal potential in this case corresponds to the comparatormid-potential. When the network interface is in single-wire operation,common mode interference resulting, for example, from an earth offsetbetween two network subscribers, cannot be completely suppressed. Thepermissible earth offset is governed by the voltage difference betweenthe terminal potential and the recessive bit level on one of two signallines.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide anetwork interface which avoids the disadvantages of the prior art.

In keeping with these objects and with others which will become apparenthereinafter, one feature of the present invention resides, brieflystated, in a network interface which has a first further means which setthe magnitude of the voltage difference between two input lines duringerror-free operation to a different magnitude for both bit levels, andin that the network interface has second further means which set theterminal potential for the respective input line in accordance with theformulae:

    UK0=(U.sub.RX1 (dom)+U.sub.RX1 (rec))/2

    and

    UK0=(U.sub.RX0 (dom)+U.sub.RX0 (rec))/2

U_(RX1) (dom) and U_(RX1) (rec) representing a respective inputpotential for one of the two bit levels on one of said input lines, andU_(RX0) (dom) and U_(RX0) (rec) representing a respective inputpotential for one of the two bit levels on the other of said inputlines.

In contrast, the network interface according to the invention having thecharacterizing features of the The network interface according to thepresent invention has the advantage that the permissible earth offset isequal and a maximum for both bit levels (recessive and dominant). Inconsequence, a greater safety margin is achieved for data transmission.This is primarily important for bus links which are intended to bedesigned to be error tolerant, for example where controllers incommercial vehicles are connected.

It is particularly advantageous to provide two controllable switches andone resistor network in the network interface, and to design theswitches such that one input line is in each case connected to one busline in its first switching state and one input line is in each caseconnected to a point on the resistor network in a second switchingstate. Single-wire operation of the network interface can thus beimplemented without any major hardware outlay. As a result of thecontrollable switches being designed such that, in their one switchingstate, they connect different input lines to different points on theresistor network, it is easily possible to connect different terminalpotentials to the input lines.

It is furthermore advantageous to design the resistor network such that,when both switches apply their terminal potential to the input line, therecessive bit level is present on the two input lines. In consequence, anetwork interface can take part in the bus traffic once again morequickly after a bus off state, irrespective of the bus traffic.Specifically, the CAN protocol specifies a minimum number of bit levelsamples with a recessive bit level before a network interface may leavea bus off state. It is likewise advantageous to provide a voltagedivider for each input line. In this way, the level changes can bematched to the operating range of the differential receiver.

The novel features which are considered as characteristic for theinvention are set forth in particular in the appended claims. Theinvention itself, however, both as to its construction and its method ofoperation, together with additional objects and advantages thereof, willbe best understood from the following description of specificembodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic illustration of a controller having a networkinterface according to the invention; FIG. 2a shows the bit levelsduring two-wire operation of the network interface according to theinvention; FIG. 2b shows the bit levels and the terminal potential for afirst single-wire mode of a network interface according to theinvention, and FIG. 2c shows the bit levels and the terminal potentialfor the second single-wire mode of the network interface according tothe invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An exemplary embodiment of the invention is illustrated in the drawingand is explained in more detail in the following description. FIG. 1illustrates a controller 10. The controller is not specified in moredetail in the following text, since this is not significant to thesubject matter of the invention. Typical controllers in the case ofwhich the invention can be used are motor vehicle controllers such asignition, injection, braking and transmission controllers etc., as wellas convenience and bodywork electronics. The controller is connected totwo bus lines 18, 19 for data interchange with further controllers. Thecontroller contains a microcomputer 11 and a network interface 12. Thenetwork interface contains a CAN chip 13. The commercially available82C200, produced by the Motorola Company, can be used, for example, asthe CAN chip 13. The microcomputer 11 and the CAN chip 13 are linked toone another via a bus. The CAN chip 13 contains a differential receiver14. A controllable switch S0 is connected to the RX0 input of thedifferential receiver 14. A controllable switch S1 is connected to theRX1 input of the differential receiver 14. Both switches S0, S1 can bedesigned as FET switches. They are connected to the microcomputer 11 viacontrol lines 16, 17. The switches S0, S1 are operated by a signal onthe control line (16, 17). Both switches S0, S1 have two switchingstates a and b. In its first switching state a, the switch S0 connectsthe RX0 input of the differential receiver 14 to a first input of afirst input of a bus coupling network 15. In its first switching statea, the switch S1 connects the RX1 input of the differential receiver 14to a second input of the bus coupling network 15. In its secondswitching state b, the switch S0 connects the RX0 input of thedifferential receiver 14 to a first point 21 on a resistor network. Inits second switching state b, the switch S1 connects the RX1 input ofthe differential receiver 14 to a second point 22 on the resistornetwork. The resistor network consists of four series-connectedresistors R1 to R4. The resistor R1 is connected to the supply voltageUB of the network interface 12, and the resistor R4 is connected toearth. The first connection point 21 of the resistor network is theconnection point between the resistors R1 and R2, and the secondconnection point 22 is the connection point between the two resistors R3and R4. The connection point between the resistors R2 and R3 isconnected to a third input of the bus coupling network 15. The buscoupling network 15 contains two voltage dividers 20. The voltagedivider 20 which is connected via the first switching state a of theswitch S0 to the RX0 input of the differential receiver, is linked tothe bus line 19. The voltage divider 20, which is connected by the firstswitching state of the switch S1 to the RX1 input of the differentialreceiver 14, is linked to the bus line 18.

The method of operation of the network interface 12, to the extent thatit is significant for the invention, is explained in the following textwith reference to FIGS. 2a to 2c. In normal operation of the networkinterface, both switches S0 and S1 are in the switching state a. If adata transmission is taking place via the bus lines 18, 19 to thenetwork interface 12, then the signal levels for the individual bits atthe RX0 input and RXl input of the differential receiver 14 appear asillustrated in FIG. 2a. The CAN differentiates between the recessive bitlevel and the dominant bit level. In this case, a recessive bit levelcan be overwritten by a dominant bit level which is likewise applied tothe bus lines 18, 19. For the specific example in FIG. 2a, the voltagelevel for the recessive bit level is 2.744 V at the RX0 input and 2.2555V at the RX1 input. The voltage levels for the dominant bit level are2.011 V at the RX0 input and 2.988 V at the RX1 input. Since thedifferential receiver 14 forms the difference between the voltage levelsat the RX0 input and the RX1 input, the bit level can be picked off viathe switching state and the output of the differential receiver 14. Innormal operation of the two-wire interface 12, common-mode interferenceon the bus lines 18, 19 has no damaging effect.

For error recognition, one network subscriber (master) transmits a testmessage, in a specific time frame, to all the other network subscribers(slaves). This is monitored by the microcomputer 11. For this purpose acounter, for example, which can also be implemented in software, can beprovided in the microcomputer 11. In normal operation, this countercontinuously counts upwards. The counter is reset only when the testmessage has been completely received, with all the error recognition,such as bit error, cyclic redundancy error check, bit stuffing error andformat error recognition has been completely received. The individualerror recognition measures are in this case carried out by the networkinterface. If the counter now exceeds a specific value, then themicrocomputer 11 interprets this as an error and then switches theswitch S0 over to the control line 16, via a signal. At this point, theterminal potential UK0=2.622 V is applied to the input line RX0.

If the bus line 19 which is assigned to this line is actuallyshort-circuited, then data reception can still take place via the intactbus line 18, as is illustrated in FIG. 2b. The differential receiver 14then switches correctly again for the recessive bit level and thedominant bit level. The terminal potential UK0 is applied to the inputline RX1 in the middle between the voltage levels for the recessive bitlevel and the dominant bit level; that is to say dU(rec)=dU(dom). Thevalue for UK0 is calculated in accordance with the formula

    UK0=(URX1(dom)+URX1(rec))/2.

If any common mode interference is now transmitted to the input lineRXl, for example as a result of an earth offset between two networksubscribers, then the data transmission is not impeded as long as it isless than dU(rec) or dU(dom).

If the bus line 19 is not short-circuited, then no data reception takesplace once again and the counter again reaches the specific value. Atthis point, the microcomputer 11 transmits signals via the control lines16, 17 to the switches S0 and S1. In consequence, they are switchedover. A terminal voltage UK1 is thus now present at the RX1 input of thedifferential receiver 14, and data reception takes place via the inputline R0. This is illustrated in FIG. 2b.

The terminal potential UK1 is applied to the input line RX0, once againin the middle between voltage levels for the recessive bit level and thedominant bit level. The value for UK1 is calculated in accordance withthe formula

    UK1=(URX0(dom)+URX0(rec))/2.

This is 2.377 V. The permissible earth offset between two networksubscribers is in this case likewise dU(rec) and dU(dom).

The voltage levels specified in FIGS. 2b and 2c for UK0 and UK1 resultwhen UB=5 V and when in addition, the resistors in the resistor networkare selected as follows:

    R1=R4=442 Ohm and R2=R3=23.3 Ohm.

If the counter now still reaches the specific value, then it has notbeen possible for the network interface to produce data reception again.This is the case, for example, when both bus lines 18, 19 are defective.In this case, the network interface 12 assumes a bus off state. In thisstate, the network interface 12 is passive, that is to say it mayneither receive data from the bus nor transmit data to the bus. Thenetwork interface 12 does not attempt to take part in the bus trafficagain until a reset request is present from the microcomputer 12.According to the CAN protocol, however, the network interface 12 mustfirst have received 11 successive bits with the recessive bit level 128times before it may transmit data to the bus again. If the reset requestis present, the microcomputer 11 switches both switches S0, S1 into theposition b. In consequence, the recessive bit level is permanentlyconnected to the differential receiver 14, and the network interface 12can quickly satisfy the condition in the CAN protocol. It thus quicklytakes part in the bus traffic again after a bus off state.

We claim:
 1. A network interface of a serial bus having at least a firstbus line and a second bus line, comprising a differential receiver; atleast a first input line and a second input line to which saiddifferential receiver is connected, each of said input lines beingconnected to one of the bus lines; means for recognizing error states ina digital transmission of data via the bus; first further means whichset a magnitude of a voltage difference between said two input lines(RX0, RX1) during error-free operation to a different magnitude for bothbit levels; second further means which set said first input line (RX1)to a first terminal potential UK0 in accordance with the formula:

    UK0=(U.sub.RX1 (dom)+U.sub.RX1 (rec))/2

if the bus line connected to said first input line (RX1) is in an errorstate, said second further means setting said second input line (RX0) toa second terminal potential UK1 in accordance with the formula:

    UK1=(U.sub.RX0 (dom)+U.sub.RX0 (rec))/2

if the bus line connected to said second input line (RX0) is in an errorstate, said first and second terminal potentials being different fromeach other such that U_(RX1) (dom) and U_(RX1) (rec) represent arespective input potential for one of the two bit levels on said firstinput line, and U_(RX0) (dom) and U_(RX0) (rec) represent a respectiveinput potential for one of the two bit levels on said second input line.2. A network interface as defined in claim 1, wherein said means forrecognizing error states in the digital transmission of data via the busis means for recognizing short circuit in the bus lines.
 3. A networkinterface as defined in claim 1, wherein said means for recognizingerror states in the digital transmission of data via the bus is meansfor recognizing interruption states in the bus lines.
 4. A networkinterface as defined in claim 1; and further comprising a plurality ofpoints of a resistor network; and means for reproducing a reception ofdata via the bus and including two controllable switches connectingrespectively at least one of said input lines to one bus line in a firstswitching state, and connecting at least one of said input lines to arespective one of said points of said resistor network in a secondswitching state.
 5. A network interface as defined in claim 4, whereinsaid switches include a first switch connecting said first input line toa first one of said points of said resistor network, while said secondswitch connects said second input line to a second one of said points ofsaid resistor network, said first point and said second point beingdifferent points of said resistor network.
 6. A network interface asdefined in claim 4, wherein said resistor network is formed so that arecessive bit level is present on said input lines when both saidswitches have been moved into the second switching state.
 7. A networkinterface as defined in claim 1; and further comprising a bus couplingnetwork connected between said input lines and the bus lines.
 8. Anetwork interface as defined in claim 7, wherein said bus couplingnetwork includes two input voltage dividers connectable to the at leasttwo bus lines.